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ASAHI KASEI
[AK4386]
100dB 96kHz 24-Bit 2ch DAC
GENERAL DESCRIPTION The AK4386 is a 24bit low voltage & low power stereo DAC. The AK4386 uses the Advanced Multi-Bit architecture, this architecture achieves DR=100dB at 3V operation. The AK4386 integrates a combination of SCF and CTF filters increasing performance for systems with excessive clock jitter. The AK4386 is suitable for the portable audio system like MP3 and the home audio systems like STB and TV, etc as low power and small package. The AK4386 is offered in a space saving 16pin TSSOP package.
AK4386
FEATURES o Sampling Rate: 8kHz 96kHz o 24-Bit 8 times FIR Digital Filter o SCF with high tolerance to clock jitter o Single-ended output buffer o Digital de-emphasis for 44.1kHz sampling o I/F Format: 24-Bit MSB justified, 16/24-Bit LSB justified, I2S Compatible o Master Clock: 512/768/1024/1536fs for Half Speed (8kHz 24kHz) 256/384/512/768fs for Normal Speed (8kHz 48kHz) 128/192/256/384fs for Double Speed (48kHz 96kHz) o CMOS Input Level o THD+N: -86dB o DR, S/N: 100dB(@VDD=3.0V) o Power Supply: 2.2 to 3.6V o Ta = -40 85C o 16pin TSSOP
TEST PDN DEM MCLK VDD
DFS1 DFS0
De-emphasis Control
Clock Divider
VSS VCOM
LRCK BICK SDTI
Audio Data Interface
8X Interpolator 8X Interpolator
Modulator Modulator
SCF CTF SCF CTF
LOUT
ROUT
DIF1
DIF0
MS0280-E-00 -1-
2003/12
ASAHI KASEI
[AK4386]
n Ordering Guide
AK4386VT AKD4386 -40 +85C 16pin TSSOP (0.65mm pitch) Evaluation Board for AK4386
n Pin Layout
MCLK BICK SDTI LRCK PDN DFS0 DFS1 DEM
1 2 3 4 5 6 7 8 Top View
16 15 14 13 12 11 10 9
TEST DIF1 VDD VSS VCOM LOUT ROUT DIF0
MS0280-E-00 -2-
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ASAHI KASEI
[AK4386]
PIN/FUNCTION
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name MCLK BICK SDTI LRCK PDN DFS0 DFS1 DEM DIF0 ROUT LOUT VCOM VSS VDD DIF1 TEST I/O I I I I I I I I I O O O I I Function Master Clock Input Pin Audio Serial Data Clock Pin Audio Serial Data Input Pin Input Channel Clock Pin Full Power Down Mode Pin "L" : Power down, "H" : Power up Sampling Speed Select 0 Pin Sampling Speed Select 1 Pin De-emphasis Filter Enable Pin "L" : OFF, "H" : ON (De-emphasis of fs=44.1kHz is enable.) Audio Interface Format 0 Pin Rch Analog Output Pin Lch Analog Output Pin Common Voltage Output Pin, 0.55 x VDD Normally connected to VSS with a 4.7F (min. 1F, max. 10F) electrolytic capacitor. Ground Pin Power Supply Pin, 2.2 3.6V Audio Interface Format 1 Pin TEST Pin This pin should be connected to VDD.
Note: All digital input pins should not be left floating.
n Handling of Unused Pin
The unused output pins should be processed appropriately as below. Classification Analog Pin Name LOUT, ROUT Setting This pin should be open.
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ASAHI KASEI
[AK4386]
ABSOLUTE MAXIMUM RATINGS
(VSS=0V; Note 1) Parameter Power Supply Input Current, Any Pin Except Supplies Digital Input Voltage Ambient Temperature (Powered applied) Storage Temperature Note 1. All voltages with respect to ground. Symbol VDD IIN VIND Ta Tstg min -0.3 -0.3 -40 -65 max 4.6 10 VDD+0.3 85 150 Units V mA V C C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note 1) Parameter Power Supply Note 1. All voltages with respect to ground. Symbol VDD min 2.2 typ 3.0 max 3.6 Units V
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
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ASAHI KASEI
[AK4386]
ANALOG CHARACTERISTICS
(Ta=25C; VDD=3.0V; VSS=0V; fs=44.1kHz, 96kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=20Hz 20kHz at fs=44.1kHz, 20Hz 40kHz at fs=96kHz; unless otherwise specified) Parameter min typ max Units Dynamic Characteristics: Resolution 24 Bits 0dBFS THD+N fs=44.1kHz -86 -76 dB -60dBFS BW=20kHz -37 dB 0dBFS fs=96kHz -84 dB -60dBFS BW=40kHz -34 dB DR (-60dBFS with A-weighted) 92 100 dB S/N (A-weighted) 92 100 dB Interchannel Isolation 80 100 dB DC Accuracy: Interchannel Gain Mismatch 0.2 0.5 dB Gain Drift 100 ppm/C Output Voltage (Note 2) 1.85 2.0 2.15 Vpp Load Resistance (Note 3) 10 k Load Capacitance 25 pF Power Supplies Power Supply Current Normal Operation (PDN pin = "H", fs=44.1kHz) Normal Operation (PDN pin = "H", fs=96kHz) Power Save mode (PDN pin = "H", MCLK Stop) Full Power-down mode (PDN pin = "L") 6 6.5 1.5 10 9 10 2.5 50 mA mA mA A
(Note 4)
Note 2. Full-scale voltage (0dB). Output voltage scales with the voltage of VDD, Vout = 0.67 x VDD (typ). Note 3. For AC-load. Note 4. All digital input pins are fixed to VDD or VSS.
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ASAHI KASEI
[AK4386]
FILTER CHARACTERISTICS
(Ta=25C; VDD=2.2 3.6V; fs=44.1kHz; DEM=OFF) Parameter Symbol DAC Digital Filter: Passband (Note 5) 0.05dB PB -6.0dB Stopband (Note 5) SB Passband Ripple PR Stopband Attenuation SA Group Delay (Note 6) GD Digital Filter + SCF + CTF: Frequency Response 0 20kHz FR 40kHz (Note 7) min 0 24.1 64 typ max 20.0 0.01 24.0 0.5 1.0 Units kHz kHz kHz dB dB 1/fs dB dB
22.05
Note 5. The passband and stopband frequencies scale with fs (system sampling rate). Note 6. The calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit data of both channels to input register to the output of analog signal. Note 7. At fs=96kHz.
DC CHARACTERISTICS
(Ta=25C; VDD=2.2 3.6V) Parameter High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Symbol VIH VIL Iin min 70%VDD typ max 30%VDD 10 Units V V A
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ASAHI KASEI
[AK4386]
SWITCHING CHARACTERISTICS
(Ta=25C; VDD=2.2 3.6V) Parameter Master Clock Frequency Half Speed Mode (512/768/1024/1536fs) Normal Speed Mode (256/384/512/768fs) Double Speed Mode (128/192/256/384fs) Duty Cycle LRCK Frequency Half Speed Mode (DFS1-0 = "10") Normal Speed Mode (DFS1-0 = "00") Double Speed Mode (DFS1-0 = "01") Duty Cycle Audio Interface Timing BICK Period Half Speed Mode Normal Speed Mode Double Speed Mode BICK Pulse Width Low Pulse Width High BICK "" to LRCK Edge LRCK Edge to BICK "" SDTI Hold Time SDTI Setup Time Power-Down & Reset Timing PDN Pulse Width Symbol fCLK fCLK fCLK dCLK fsh fsn fsd dCLK min 4.096 2.048 6.144 40 8 8 48 45 typ max 36.864 36.864 36.864 60 24 48 96 55 Units MHz MHz MHz % kHz kHz kHz %
(Note 8) (Note 8)
tBCK tBCK tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS tPD
1/128fs 1/128fs 1/64fs 70 70 40 40 40 40 4xC
ns ns ns ns ns ns ns ns ns ms
(Note 9)
Note 8. BICK rising edge must not occur at the same time as LRCK edge. Note 9. The AK4386 can be reset by bringing PDN pin = "L". The PDN pulse width is proportional to the value of the capacitor (C) connected to VCOM pin. tPD = 4 x C. When C = 4.7F, tPD is 19ms(min). The value of the capacitor (C) connected with VCOM pin should be 1F C 10F. When the states of DIF1-0 pins change, the AK4386 should be reset by PDN pin.
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ASAHI KASEI
[AK4386]
n Timing Diagram
1/fCLK VIH VIL tCLKH tCLKL
MCLK
1/fs VIH VIL
LRCK
tBCK VIH VIL tBCKH tBCKL
BICK
Clock Timing
VIH LRCK VIL tBLR tLRB VIH BICK VIL tSDS tSDH VIH SDTI VIL
Audio Interface Timing
tPD PDN VIL
Power Down & Reset Timing
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2003/12
ASAHI KASEI
[AK4386]
OPERATION OVERVIEW n System Clock
The external clocks, which are required to operate the AK4386, are MCLK, BICK and LRCK. The master clock (MCLK) should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the delta-sigma modulator. The MCLK frequency is detected from the relation between MCLK and LRCK automatically. The Half speed, the Normal speed and the Double speed mode are selected with the DFS1-0 pins (Table 1). The sampling speed mode is set depending on the MCLK frequency automatically for Auto mode (DFS1 pin = DFS0 pin = "H") (Table 2). The AK4386 is automatically placed in the power save mode when MCLK stops in the normal operation mode (PDN pin = "H"), and the analog output becomes the VCOM voltage. After MCLK is input again, the AK4386 is powered up. After exiting reset at power-up etc., the AK4386 is in the power-down mode until MCLK and LRCK are input. When the states of DIF1-0 pins change in the normal operation mode, the AK4386 should be reset by PDN pin. Mode Normal Speed Double Speed Half Speed Auto DFS1 L L H H DFS0 fs L 8 48kHz H 48 96kHz L 8 24kHz H 8 96kHz Table 1. System Clock Example Sampling Speed Mode Normal Speed Double Speed Half Speed Table 2. Auto Mode MCLK Frequency 256/384/512/768fs 128/192/256/384fs 512/768/1024/1536fs Table 2
MCLK Frequency 512/768fs 128/192/256/384fs 1024/1536fs
fs 8 48kHz 48 96kHz 8 24kHz
n Audio Interface Format
Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF1-0 pins as shown in Table 3 can select four serial data modes. In all modes the serial data is MSB-first, 2's compliment format and is latched on the rising edge of BICK. Mode 3 can be used for 16bit I2S Compatible format by zeroing the unused LSBs at BICK 48fs or BICK = 32fs. Mode 0 1 2 3 DIF1 L L H H DIF0 SDTI Format L 16bit, LSB justified H 24bit, LSB justified L 24bit, MSB justified H 16/24bit, I2S Compatible Table 3. Audio Interface Format BICK 32fs 48fs 48fs 48fs or 32fs Figure Figure 1 Figure 2 Figure 3 Figure 4
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2003/12
ASAHI KASEI
[AK4386]
LRCK
0123 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1
BICK(32fs) SDTI(i) BICK(64fs) SDTI(i)
Don't Care 15 14 13 12 10 Don't Care 15 14 13 12 210 15 14 13 0123 7 6 5 4 3 2 1 0 15 14 13 17 18 19 20 31 0 1 2 3 7 6 5 4 3 2 1 0 15 17 18 19 20 31 0 1
SDTI-15:MSB, 0:LSB Lch Data Rch Data
Figure 1. Mode 0 Timing
LRCK
012 89 24 31 0 1 2 89 24 31 0 1
BICK(64fs) SDTI(i)
Don't Care 23:MSB, 0:LSB Lch Data Rch Data 23 8 10 Don't Care 23 8 10
Figure 2. Mode 1 Timing
LRCK
012 20 21 22 23 24 31 0 1 2 20 21 22 23 24 31 0 1
BICK(64fs) SDTI(i)
23 22 4 3 2 1 0 Don't Care 23 22 43210 Don't Care 23
23:MSB, 0:LSB Lch Data Rch Data
Figure 3. Mode 2 Timing
LRCK
0123 21 22 23 24 25 012 21 22 23 24 25 01
BICK(64fs) SDTI(i)
23 22 4 3 2 1 0 Don't Care 23 22 43210 Don't Care
23:MSB, 0:LSB Lch Data Rch Data
Figure 4. Mode 3 Timing
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2003/12
ASAHI KASEI
[AK4386]
n De-emphasis Filter
The AK4386 includes the digital de-emphasis filter (tc=50/15s) by IIR filter. This filter corresponds to 44.1kHz sampling. The de-emphasis filter is enabled by setting DEM pin "H". In case of Half speed and Double speed mode, the digital de-emphasis filter is always off. DFS1 pin DFS0 pin DEM pin De-emphasis Filter L L L OFF Normal Speed L L H ON Double Speed L H * OFF Half Speed H L * OFF H H L OFF Auto H H H ON (Note) Table 4. De-emephasis Filter (*: Don't care) Note. The digital de-emphasis filter corresponds to 44.1kHz sampling. In case of Half speed and Double speed mode, the digital de-emphasis filter is always off. Mode
n Power-down
The AK4386 is placed in the power-down mode by bringing PDN pin = "L". and the digital filter is reset at the same time. This reset should always be done after power up. When PDN pin = "L", DAC outputs go to Hi-Z. Also, the internal power down is automatically done when MCLK stops during operating (PDN pin ="H"), and the analog outputs go to the VCOM voltage. MCLK pin should be fixed to "H" or "L" when MCLK stops. Mode 0 1 2 PDN pin L H MCLK DAC Output Don't care Hi-Z Supplied Normal Output Not Supplied VCOM Voltage Table 5. Power down mode State Full Power Down Normal Power Save
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ASAHI KASEI
[AK4386]
(1) Power down by PDN pin
PDN
Internal State D/A In (Digital)
GD
(1)
Normal Operation
Power-down
Normal Operation
"0" data
(2) (4) (3) (4)
GD
(2)
D/A Out (Analog)
Clock In
MCLK, BICK, LRCK
(5) Don't care (6)
External MUTE
Mute ON
Notes: (1) PDN pin should be "L" for 19ms or more when an electrolytic capacitor 4.7F is attached between VCOM pin and VSS.) (2) The analog output corresponding to digital input has the group delay (GD). (3) When PDN pin = "L", the analog output is Hi-Z. (4) Click noise occurs in 3 4LRCK at both edges ( ) of PDN signal. This noise is output even if "0" data is input. (5) The external clocks (MCLK, BICK and LRCK) can be stopped in the power down mode (PDN pin = "L"). (6) Please mute the analog output externally if the click noise (4) influences system application. The timing example is shown in this figure. Figure 5. Power-down/up sequence example 1
MS0280-E-00 - 12 -
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ASAHI KASEI
[AK4386]
(2) Power save by MCLK stop (PDN pin = "H")
PDN pin
Internal State D/A In (Digital) D/A Out (Analog)
Clock In
MCLK, BICK, LRCK
(1)
Power-down
Normal Operation
Power-save
Normal Operation
Power-down GD Hi-Z
(3) (2) (4) (4) (5) MCLK Stop
VCOM GD
(2)
(4)
External MUTE
(5)
(6)
(6)
Notes: (1) PDN pin should be "L" for 19ms or more when an electrolytic capacitor 4.7F is attached between VCOM pin and VSS.) (2) The analog output corresponding to digital input has the group delay (GD). (3) The digital data can be stopped. The click noise after MCLK is input again by inputting the "0" data to this section can be reduced. (4) Click noise occurs in 3 4LRCK at both edges ( ) of PDN signal, MCLK inputs and MCLK stops. This noise is output even if "0" data is input. (5) The external clocks (BICK and LRCK) can be stopped in the power down mode (MCLK stop). (6) Please mute the analog output externally if the click noise (4) influences system application. The timing example is shown in this figure. Figure 6. Power-down/up sequence example 2
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ASAHI KASEI
[AK4386]
SYSTEM DESIGN
Figure 7 shows the system connection diagram. An evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results.
Master Clock 64fs 24bit Audio Data fs Reset & Power down Mode Setting
1 2 3 4 5 6 7 8
MCLK BICK SDTI LRCK PDN DFS0 DFS1 DEM
TEST DIF1 VDD
16 15 14 0.1u 13 4.7u 12 11 10 9 + (C) + 10u
Analog Supply 2.2 to 3.6V
AK4386
VSS VCOM LOUT ROUT DIF0
Lch Out MUTE Rch Out
Digital Ground
Analog Ground
Note: - VSS of the AK4386 should be distributed separately from the ground of external digital devices (MPU, DSP etc.). - When AOUT drive some capacitive load, some resistor should be added in series between AOUT and capacitive load. - The value of the capacitor connected to VCOM pin should be 1F C 10F. - All digital input pins should not be left floating. Figure 7. Typical Connection Diagram
1. Grounding and Power Supply Decoupling The AK4386 requires careful attention to power supply and grounding arrangements. VDD is usually supplied from the analog supply in the system. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4386 as possible, with the small value ceramic capacitor being the closest. 2. Voltage Reference The differential Voltage between VDD and VSS sets the analog output range. VCOM is used as a common voltage of the analog signal. VCOM pin is a signal ground of this chip. An electrolytic capacitor about 4.7F should be attached between VCOM pin and VSS. No load current may be drawn from VCOM pin. Especially, the ceramic capacitor should be connected to this pin as near as possible. 3. Analog Outputs The analog outputs are single-ended and centered around the VCOM voltage (0.55 x VDD). The output signal range is typically 2.0Vpp (typ@VDD=3.0V). The internal switched-capacitor filter and continuous-time filter attenuate the noise generated by the delta-sigma modulator beyond the audio passband. The output voltage is a positive full scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal output is VCOM voltage (0.55 x VDD) for 000000H (@24bit). DC offsets on analog outputs are eliminated by AC coupling since analog outputs have DC offsets of VCOM + a few mV.
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2003/12
ASAHI KASEI
[AK4386]
PACKAGE
16pin TSSOP (Unit: mm)
5.0 1.10max
16
9 A 6.40.2 0.170.05 0.10.1 Detail A 0.50.2 0.10 010
Epoxy Cu Solder (Pb free) plate 2003/12 - 15 -
1 0.220.1
8 0.65
Seating Plane
n Material & Lead finish
Package molding compound: Lead frame material: Lead frame surface treatment:
MS0280-E-00
4.4
ASAHI KASEI
[AK4386]
MARKING
AKM 4386VT XXYYY
1) 2)
3)
Pin #1 indication Date Code : XXYYY (5 digits) XX: Lot# YYY: Date Code Marketing Code : 4386VT
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
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